A fin channel MISFET (FinFET) structure and nano-wire channel transistor (nanowire transistor) with enhanced tolerance against short-channel effects are expected to be used as a device structure for realizing ultra-highly scaled down metal insulator semiconductor field effect transistors (MISFETs) with gate length of 30 nanometers (nm) or less. The FinFET is designed, for example, to have on a silicon substrate a rectangular solid-shaped semiconductor layer, one part of which is used as a channel region. On both side faces of this channel region, a gate electrode is formed so that thin channel region is interposed therebetween. This gate electrode is structured to surround the channel region; so, the gate controllability is improved, and the short-channel effect tolerance is enhanced.
A nanowire transistor is similar in structure to the FinFET with the rectangular solid-shaped semiconductor layer being reduced in height and also with the gate electrode being also provided on a top surface of the rectangular solid-like semiconductor layer. In the nanowire transistor, the top surface of the rectangular semiconductor layer also operates as the channel. A nanowire transistor having its rectangular semiconductor layer of a relatively large size is also called the “tri-gate” transistor.
On the other hand, in order to improve the operation speed of the existing planar MISFETs, there is a technique for introducing crystal lattice distortion or strain into a channel from a gate electrode. This is known as the gate-induced strain technique, which is disclosed in K. Ota et al., “Novel Locally Strained Channel Technique for High Performance 55 nm CMOS,” IEDM Tech. Digest, pp. 27-30 (2002). For example, a chosen impurity, such as phosphorus (P), arsenic (As), germanium (Ge) or else, is heavily doped into a polycrystalline silicon (poly-Si) gate electrode to a high concentration and form a stress liner nitride film on the poly-Si gate electrode. While this high concentration impurity doping results in the poly-Si gate electrode being converted to an amorphous state, i.e., amorphasized, it must experience crystallization during annealing at high temperatures so that volume expansion takes place. As the volume expansion of the poly-Si gate electrode is suppressed by the presence of its overlying stress liner nitride film, a compressive stress is accumulated in the poly-Si gate electrode. The stress linear nitride film is removed away after completion of the annealing process. However, even after this film removal, the compressive stress that was generated in the poly-Si gate electrode continues to exist in the form of a grain size(s).
Upon occurrence of the compressive stress in the poly-Si gate electrode, a compressive strain is induced in the channel region in a direction at right angles to the substrate whereas an extensional or tensile strain is induced in a direction along the gate length. The strain in this direction contributes to an improvement in performance of n-channel MISFETs (nMISFETs); so, attempts are vigorously made to introduce it into nMISFETs. Note however that no such attempts result in improvement in performance of p-channel MISFETs (pMISFETs). This method is called the stress memorization technique (SMT) in light of its feature that a stress is left or “memorized” in the poly-Si gate electrode even after having removed the stress linear nitride film.
In the sub-30 nm generation of device technology, it is considered desirable to apply the SMT to FinFETs or nanowire transistors. However, there has not been given any definite guideline for the strain to be applied to the channel region of a FinFET or a nanowire transistor in order to improve the transistor characteristics. Accordingly, the SMT that is best suited for FinFETs or nanowire transistors is not yet established until today.